Modern integrated circuits are typically constructed in a thin layer in a semiconducting layer on a substrate wafer such as silicon. This essentially two-dimensional structure limits both the size of the integrated circuit and the speed at which the circuit operates. The speed at which an integrated circuit operates is determined by the distance between the farthest separated components that must communicate with one another on the chip. For any given number of components, the path lengths will, in general, be significantly reduced if the circuit can be laid out as a three dimensional structure consisting of a number of vertically-stacked layers of circuitry, provided the vertical distances between the layers are much smaller than the width of the chips that make up the individual layers.
One promising scheme for providing such stacked structures utilizes a method for stacking and bonding entire wafers. In this method, integrated circuits are fabricated on conventional wafers. Two wafers are bonded vertically by thinning one wafer in a first coarse thinning operation by removing material from the back of the wafer. The circuitry on the front surface of each wafer is covered with an insulating layer having metal filled vias that make contact with the underlying circuitry and act as electrical connection points between the two wafers. In addition, the front surfaces of the wafers include bonding pads that are planar metal areas that do not connect to the underlying circuitry. The bonding pads are provided to increase the bonded area. The front surfaces of the wafers are then placed in contact with one another so that the bonding pads on one wafer are in contact with the pads on the other wafer. Thermal diffusion bonding is then used to bond the metal pads, and hence, the wafers together. One of the wafers is then further thinned to a thickness of a few microns by etching or mechanically grinding the back surface of that wafer further. Once the wafer has been thinned, a new set of vias is opened in the backside and filled with metal to provide the connection points to the pads on the front side of the wafer that make connections with the circuitry in the wafer. In addition, a new set of bonding pads is formed on the backside of the wafer so that another wafer can be bonded to the stack. The process is then repeated until the desired number of layers has been bonded to form the three-dimensional stack. The three-dimensional stack is then cut into three-dimensional chips and packaged.
Each time a top wafer in the stack is thinned, the wafers below that wafer are subjected to a significant amount of lateral stress by the grinding process. Accordingly, the bonds that hold the wafers together must withstand these large stresses. In principle, the ability of the wafers to withstand these stresses can be increased by increasing the bond area, i.e., devoting more area to bonding pads between the wafers. Unfortunately, this approach has the drawback of reducing the number of vertical conductors that can be provided in circuits requiring a high density of inter-layer vertical conductors.
This process also requires a considerable amount of “backside processing” to provide the new set of contacts on the backside of the wafer. The generation of the vertical conductors requires a number of masking and deposition steps. Each conductor is structurally similar to a golf tee. The “head” of the tee provides the area needed to accommodate alignment errors. Separate mask and deposition steps are required to etch the via that forms the stem of the tee and the head that sits on this stem. The via must also be lined to prevent diffusion of the metal into the surrounding silicon. Such extensive backside processing can substantially reduce the yield of stacked wafers.
The situation is made more complicated by the lack of fiduciary marks on the backside of the thinned wafer. Hence, precise alignment of the masks that define the locations of the vias with respect to the circuitry on the front side of the wafer is difficult. Misalignment of these vias leads to defects that render the entire stack of chips useless. In addition, the semiconductor processing steps required by the backside processing of the top layer subject the underlying layers to thermal and mechanical stresses that are repeated with each new layer.
Broadly, it is the object of the present invention to provide an improved method for stacking and thinning wafers to generate a three-dimensional integrated circuit.
It is a further object of the present invention to provide a method that eliminates the backside processing steps utilized in prior art stacking techniques.
These and other objects of the present invention will become apparent to those skilled in the art from the following detailed description of the invention and the accompanying drawings.